Efficient Complexity Reduction Technique for Parallel FIR Digital Filter based on Fast FIR Algorithm

The objective of the paper is to reduce the hardware complexity of higher order FIR filter with symmetric coefficients. The aim is to design an efficient Fast Finite-Impulse Response (FIR) Algorithms (FFAs) for parallel FIR filter structure, with a constrain that the filter tap must be multiple of 2. In our work we have briefly discussed for L=4 parallel implementation. The parallel FIR filter structure based on proposed FFA technique has been implemented based on carry save and ripple carry adder for further optimization. The reduction in silicon area complexity is achieved by eliminating the bulky multiplier with an adder namely ripple carry and carry save adder. For an example, a 6-parallel 1024-tap filter, the proposed structure saves 14 multiplier at the expanse of 10 adders, whereas for a six-parallel 512-tap filter, the proposed structure saves 108 multiplier at the expense of 10 adders still. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric coefficients from the existing FFA parallel FIR filter, especially when the length of the filter is very large.